Nonvolatile semiconductor memory device having improved redundancy relieving rate

ABSTRACT

In a memory cell array of an MRAM, a normal memory cell is compared with a reference memory cell which holds a reference value, thereby storing data of one bit per cell. Two spare memory cells store data of one bit as a whole. By writing complementary values to the two spare memory cells and connecting these spare memory cells to a sense amplifier, the stored data of one bit is read. A spare memory cell section which is often arranged in an array peripheral portion becomes more resistant against a variation in finished dimensions of elements and a success rate for replacing and relieving a defective memory cell by a spare memory cell increases.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a nonvolatile semiconductormemory device, and more particularly to a nonvolatile semiconductormemory device including a spare memory cell for replacing a defectivememory cell.

[0003] 2. Description of the Background Art

[0004] For a semiconductor memory device which executes data storage,various data storage formats are employed to store data in memory cells.For example, there is provided a semiconductor memory device constitutedso that the pass current of each memory cell changes according to datastored in the memory cell when the memory cell is accessed. In thesemiconductor memory device of this type, the data stored in a selectedmemory cell is read in accordance with the comparison between the passcurrent of the selected memory cell to be accessed and a presetreference current. As semiconductor memory devices having such memorycells, attention is being paid to an MRAM (Magnetic Random AccessMemory) device capable of executing the storage of nonvolatile data withlow power consumption.

[0005] Recently, in particular, it has been made public that theperformance of an MRAM device dramatically advances by employing thinfilm magnetic elements using MTJs (Magnetic Tunnel Junctions) as memorycells. The MRAM device which includes memory cells each having the MTJsis disclosed, for example, in the following technical documents:

[0006] Roy Scheuerlein and six others, “A 10 ns Read and WriteNon-Volatile Memory Array Using a Magnetic Tunnel Junction and FETSwitch in each Cell”, ISSCC Digest of Technical Papers, February 2000,TA7.2, pp. 94-95, 128-129 and 409.

[0007] M. Durlam and five others, “Nonvolatile RAM based on MagneticTunnel Junction Elements”, ISSCC Digest of Technical Papers, February2000, TA7.3, pp. 96-97.

[0008]FIG. 18 is a schematic diagram showing a configuration of a memorycell which has a tunnel junction (hereinafter, also simply referred toas “MTJ memory cell”).

[0009] With reference to FIG. 18, the MTJ memory cell includes atunneling magneto-resistance element TMR having electric resistancewhich changes in accordance with the data level of magnetically writtenstorage data, and an access transistor ATR. Access transistor ATR isconnected in series to tunneling magneto-resistance element TMR betweena write bit line WBL and a read bit line RBL. As access transistor ATR,a field effect transistor formed on a semiconductor substrate istypically employed.

[0010] For the MTJ memory cell, write bit line WBL and write digit lineWDL each for carrying data write currents in different directions duringdata write, a word line WL for instructing data read, and read bit lineRBL receiving the supply of the data read currents are provided. Duringdata read, in response to turning on access transistor ATR, tunnelingmagneto-resistance element TMR is electrically coupled between write bitline WBL set at a ground voltage GND and read bit line RBL.

[0011]FIG. 19 is a conceptual view for describing a data write operationfor writing data to the MTJ memory cell.

[0012] With reference to FIG. 19, tunneling magneto-resistance elementTMR includes a ferromagnetic material layer FL which has a fixedconstant magnetic direction (hereinafter, also simply referred to as“fixed magnetic layer”) and a ferromagnetic material layer VL which ismagnetized in a direction according to a magnetic field applied fromexternally (hereinafter, also simply referred to as “free magneticlayer”). A tunneling barrier (tunneling film) TB formed from aninsulating film is provided between fixed magnetic layer FL and freemagnetic layer VL. Free magnetic layer VL is magnetized in the samedirection or the opposite direction to that of fixed magnetic layer FLin accordance with the level of stored data to be written. Fixedmagnetic layer FL, tunneling barrier TB and free magnetic layer VL forma magnetic tunnel junction.

[0013] The electric resistance of tunneling magneto-resistance elementTMR changes according to the relative relationship between the magneticdirection of fixed magnetic layer FL and that of free magnetic layer VL.Specifically, if the magnetic direction of fixed magnetic layer FL isparallel to that of free magnetic layer VL, the electric resistancevalue of tunneling magneto-resistance element TMR is a minimum valueRmin. If these magnetic directions are opposite (non-parallel) to eachother, the electric resistance value of tunneling magneto-resistanceelement TMR is a maximum value Rmax.

[0014] During data write, word line WL is deactivated and accesstransistor ATR is turned off. In this state, a data write current formagnetizing free magnetic layer VL is carried to each of bit line BL andwrite digit line WDL in a direction according to the level of the writedata.

[0015]FIG. 20 is a conceptual view for describing the relationshipbetween the data write current and the magnetic direction of a tunnelingmagneto-resistance element during data write.

[0016] With reference to FIG. 20, the horizontal axis indicates amagnetic field applied in an easy axis (EA: Easy Axis) direction in freemagnetic layer VL in tunneling magneto-resistance element TMR. Thevertical axis H(HA) indicates a magnetic field applied in a hard axis(HA: Hard Axis) direction in free magnetic layer VL. Magnetic fieldsH(EA) and H(HA) correspond to two magnetic fields generated by currentscarried to bit line BL and write digit line WDL, respectively.

[0017] In the MTJ memory cell, the fixed magnetic direction of fixedmagnetic layer FL is along the easy axis of free magnetic layer VL. Freemagnetic layer VL is magnetized in a direction parallel or non-parallel(opposite) to fixed magnetic layer FL along the easy axis direction inaccordance with the level of stored data (“1” or “0”). The MTJ memorycell can store 1-bit data (“1” and “0”) corresponding to the twomagnetic directions of free magnetic layer VL.

[0018] The magnetic direction of free magnetic layer VL can be rewrittenonly when the sum of magnetic fields H(EA) and H(HA) applied to freemagnetic layer VL reaches a region outside of an asteroid characteristicline shown in FIG. 20. In other words, when the data write magneticfield applied to free magnetic layer VL has an intensity correspondingto the region inside of the asteroid characteristic line, the magneticdirection of free magnetic layer VL has no change.

[0019] As shown in the asteroid characteristic line, if a magnetic fieldin the hard axis direction is applied to free magnetic layer VL, it ispossible to decrease a magnetc threshold necessary to change themagnetic direction of free magnetic layer VL along the easy axis.

[0020] If operation points during data write are designed as shown inthe example of FIG. 20, the data write magnetic field in the easy axisdirection is designed so as to have an intensity of H_(WR) in the MTJmemory cell to which the data is to be written. That is, the value ofthe data write current carried to each of bit line BL and write digitline WDL is designed so as to obtain this data write magnetic fieldH_(WR). Generally, data write magnetic field H_(WR) is expressed by thesum of a switching magnetic field H_(SW) necessary to change over amagnetic direction and a margin ΔH, i.e., H_(WR)=H_(SR)+ΔH.

[0021] In order to rewrite the stored data of the MTJ memory cell, i.e.,to rewrite the magnetic direction of tunneling magneto-resistanceelement TMR, it is necessary to carry a data write current atpredetermined level or higher to each of write digit line WDL and bitline BL. Thereby, free magnetic layer VL in tunneling magneto-resistanceelement TMR is magnetized in the direction parallel or opposite(non-parallel) to that of fixed magnetic layer FL in accordance with thedirection of the data write magnetic field along the easy axis (EA). Themagnetic direction which is written to tunneling magneto-resistanceelement TMR once, i.e., the stored data of the MTJ memory cell is heldin a nonvolatile manner until new data is written.

[0022]FIG. 21 is a conceptual view for describing a data read operationfor reading data from the MTJ memory cell.

[0023] With reference to FIG. 21, during data read, access transistorATR is turned on in response to the activation of word line WL. Writebit line WBL is set at ground voltage GND. As a result, tunnelingmagneto-resistance element TMR is electrically coupled to read bit lineRBL while being pulled down at ground voltage GND.

[0024] In this state, if read bit line RBL is pulled up at apredetermined voltage, a memory cell current Icell according to theelectric resistance of tunneling magneto-resistance element TMR, i.e.,according to the level of the stored data in the MTJ memory cell, passesthrough a current path which includes read bit line RBL and tunnelingmagneto-resistance element TMR. By comparing this memory cell currentIcell with a predetermined current, for example, it is possible to readthe data stored in the MTJ memory cell.

[0025] As described above, the electric resistance of tunnelingmagneto-resistance element TMR changes according to the magneticdirection which can be rewritten by the data write magnetic fieldapplied thereto. Therefore, if electric resistance values Rmax and Rminof tunneling magneto-resistance element TMR are made to correspond tothe levels (“1” and “0”) of the stored data, respectively, it ispossible to store nonvolatile data.

[0026] An MRAM of 1 transistor-1 MTJ element type as shown in FIG. 18,however, sometimes causes a malfunction depending on the finished statesof memory cell elements. Due to this, redundant memory cells are oftenprovided in preparation for an instance in which a failure such as amalfunction generates to a normal memory cell. If a defective memorycell is discovered and this defective memory cell is replaced by a sparememory cell, a chip which has been determined to be a failure chip oncecan be relieved.

[0027] Nevertheless, the spare memory cells are often provided in aportion peripheral of a memory cell array. If the spare memory cells arelocated in such a peripheral portion, the finished dimensions ofelements tend to exhibit a wide range of variation compared with thecentral portion of the memory cell array. If a spare memory cell isdefective, a chip cannot be relieved even by replacing a defectivememory cell by the spare memory cell.

SUMMARY OF THE INVENTION

[0028] It is an object of the present invention to provide a nonvolatilesemiconductor memory device capable of improving the reliability of aspare memory cell and operating at high rate.

[0029] In short, the present invention provides a nonvolatilesemiconductor memory device including: a plurality of normal memorycells each storing data of one bit in a nonvolatile manner; a pluralityof spare memory cells each used in place of a defective memory cell whenthe defective memory cell is present in the plurality of normal memorycells, and constituted so that two spare memory cells store data of onebit as a whole; a control circuit, in accordance with an externalaccess, selecting a first memory cell group corresponding to an addresssignal from among the plurality of normal memory cells and selecting asecond memory cell group from among the plurality of spare memory cellsin parallel to selection of the first memory cell group; and a selectand amplification section selecting a read memory cell group inaccordance with the address signal from among the first and secondmemory cell groups, and amplifying and outputting the data held in theread memory cell group.

[0030] Therefore, a main advantage of the present invention is asfollows. Since the two spare memory cells store data of one bit as awhole, a spare memory cell section which is often arranged in an arrayperipheral portion becomes more resistant against a variation infinished dimensions of elements and a success rate for replacing andrelieving a defective memory cell by a spare memory cell increases.

[0031] The foregoing and other objects, features, aspects and advantagesof the present invention will become more apparent from the followingdetailed description of the present invention when taken in conjunctionwith the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0032]FIG. 1 is a schematic block diagram showing the configuration of anonvolatile semiconductor memory device 1 according to a firstembodiment of the present invention;

[0033]FIG. 2 is a block diagram for describing a data read system ofnonvolatile semiconductor memory device 1 shown in FIG. 1;

[0034]FIG. 3 is a block diagram for describing a data write system ofnonvolatile semiconductor memory device 1 shown in FIG. 1;

[0035]FIG. 4 is a circuit diagram showing the configurations of the readand write systems of nonvolatile semiconductor memory device 1 shown inFIGS. 2 and 3 in more detail;

[0036]FIG. 5 is a circuit diagram for describing an example of a circuitwhich controls deactivation when a spare memory cell is selected in awrite driver 131;

[0037]FIG. 6 is a circuit diagram showing the configuration of a programarray 36 shown in FIG. 1;

[0038]FIG. 7 shows the change of the resistance value of a normal MTJelement;

[0039]FIG. 8 shows the change of the resistance value of the MTJ elementwhich has data fixed;

[0040]FIG. 9 is a circuit diagram showing the configuration of a CAMarray 38 shown in FIG. 1;

[0041]FIG. 10 is a circuit diagram showing the configuration of aconsistency detection section 431 shown in FIG. 9;

[0042]FIG. 11 is a circuit diagram showing the configuration of a selectand amplification section 40 shown in FIG. 1;

[0043]FIG. 12 shows the configuration of a data read system of anonvolatile semiconductor memory device according to a second embodimentof the present invention;

[0044]FIG. 13 is a circuit diagram for describing a memory array 10 aand a spare memory array 12 a described with reference to FIG. 12 inmore detail;

[0045]FIG. 14 is a plan view showing the shapes of memory cells in aphase-changing memory;

[0046]FIG. 15 is a cross-sectional view taken along line A-A of FIG. 14;

[0047]FIG. 16 is an equivalent circuit diagram of the memory cell arrayshown in FIG. 14;

[0048]FIG. 17 is a circuit diagram showing a case where the presentinvention is applied to a phase-changing memory;

[0049]FIG. 18 is a schematic diagram showing the configuration of amemory cell having a tunnel junction;

[0050]FIG. 19 is a conceptual view for describing a data write operationfor writing data to an MTJ memory cell;

[0051]FIG. 20 is a conceptual view for describing the relationshipbetween a data write current and the magnetic direction of a tunnelingmagneto-resistance element during data write; and

[0052]FIG. 21 is a conceptual view for describing a data read operationfor reading data from the MTJ memory cell.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0053] Hereinafter, embodiments of the present invention will bedescribed in detail with reference to the drawings. It is noted that thesame or corresponding elements are denoted by the same reference symbolsin the drawings.

[0054] First Embodiment

[0055]FIG. 1 is a schematic block diagram showing the configuration of anonvolatile semiconductor memory device 1 according to a firstembodiment of the present invention.

[0056] With reference to FIG. 1, nonvolatile semiconductor memory device1 randomly accesses a memory cell in response to an external controlsignal CMD and an external address signal ADD and executes the input ofwrite data DIN and the output of read data DAT.

[0057] Nonvolatile semiconductor memory device 1 includes a controlcircuit 5 which controls the entire operation of nonvolatilesemiconductor memory device 1 in accordance with control signal CMD, anda memory array 10 which includes MTJ memory cells MC arranged in amatrix.

[0058] In memory array 10, word lines WL and write digit lines WDL arearranged to correspond to the respective rows of the MTJ memory cells.In addition, bit lines BL and source lines SL are arranged to correspondto the respective columns of the MTJ memory cells MC. FIG. 1 typicallyshows the arrangement of one MTJ memory cell MC, and one word line WL,one write digit line WDL, one bit line BL and one source line SLcorrespond to MTJ memory cell MC.

[0059] Nonvolatile semiconductor memory device 1 also includes a rowdecoder 20 which decodes a row address RA shown by an address signal andexecutes row selection in memory array 10, a column decoder 25 whichdecodes a column address CA shown by address signal ADD and executescolumn selection in memory array 10, and a read/write control circuit30.

[0060] Read/write control current 30 generically expresses a circuit forcarrying a data write current to bit line BL during data write and acircuit for carrying a data read current to bit line BL during dataread.

[0061] Nonvolatile semiconductor memory device 1 further includes aspare memory array 12 provided adjacent to memory array 10, and aredundancy select section 32. Spare memory array 12 shares word line WLand write digit line WDL with memory array 10. Redundancy select section32 selects a part of a plurality of spare bit lines SBL included inspare memory array 12.

[0062] Further, nonvolatile semiconductor memory device 1 includes a pad34 for applying a predetermined high potential SVCC from externally, aCAM (Content Addressable Memory) array 38 to which replacement addressinformation is transferred from program array 36, and a select andamplification section 40.

[0063] The replacement address information which is held in programarray 36 in a nonvolatile manner is transferred to CAM array 38 when apower supply is turned on. CAM array 38 compares the transferredreplacement address information with input address information ADD athigh rate, and outputs a control signal RCON. Redundancy select section32 selects a part of a plurality of spare bit lines SBL in accordancewith control signal RCON. Select and amplification section 40 selectsread data transmitted from read/write control circuit 30 and redundancyselect section 32 in accordance with control signal RCON and outputsread data DAT.

[0064] Control circuit 5, row decoder 20, column decoder 25, read/writecontrol circuit 30, CAM array 38 and redundancy select section 32 form aselect control circuit of nonvolatile semiconductor memory device 1 as awhole. This select control circuit selects a first memory cell groupcorresponding to address signal ADD from among a plurality of normalmemory cells in accordance with an external access. In parallel to theselection of the first memory cell group, the select control circuitselects a second memory cell group from among a plurality of sparememory cells. By selecting spare memory cells in parallel to the normalmemory cells, a read operation rate is accelerated.

[0065]FIG. 2 is a block diagram for describing a data read system ofnonvolatile semiconductor memory device 1 shown in FIG. 1.

[0066] With reference to FIG. 2, memory array 10 includes normal memorycell blocks 51 to 53 and reference cell columns 61 to 63. The data readfrom normal memory cell blocks 51 to 53 is compared with a referencevalue which corresponds to an intermediate level between a high leveland a low level held in reference cell columns 61 to 63, respectively,whereby the data stored in each memory cell is determined.

[0067] Spare memory array 12 includes spare memory cell columns 71 to73. Two memory cells store data of one bit as a whole in each sparememory cell. Therefore, compared with normal memory cells each of whichstores data of one bit, the reliability of the spare memory cells isimproved.

[0068] Selectors 81 to 83 are provided to correspond to normal memoryblocks 51 to 53, respectively. In addition, IO line pairs IOP1 to IOP3are provided to correspond to normal memory cell blocks 51 to 53,respectively.

[0069] The output of selector 81 is connected to one of the IO lines inIO line pair IOP1 by a connection section 91, and that of reference cellcolumn 61 is connected to the other IO line in IO line pair IOP1 by aconnection section 92.

[0070] The output of selector 82 is connected to one of the IO lines inIO line pair IOP2 by a connection section 93, and that of reference cellcolumn 62 is connected to the other IO line in IO line pair IOP2 by aconnection section 94.

[0071] The output of selector 83 is connected to one of the IO lines inIO line pair IOP3 by a connection section 95, and that of reference cellcolumn 63 is connected to the other IO line in IO line pair IOP1 by aconnection section 96.

[0072] While FIG. 2 shows a case where the three IO line pairs and thethree normal memory blocks are provided, the number of IO line pairs andthat of normal memory blocks may be larger or smaller than 3 as long asthe number of normal memory blocks is equal to that of the correspondingIO line pairs. An accessed memory cell in a normal memory cell block isconnected to one of the IO line in an IO line pair, and a memory cell inthe corresponding reference cell column is connected to the other IOline in the IO line pair.

[0073] A part of spare memory cell columns 71 to 73 are selected by aselector 84. Selector 84 selects two out of the three spare memory cellcolumns in accordance with control signal RCON outputted from CAM array38 shown in FIG. 1, and connects the two selected spare cell columns totwo IO line pairs IOP4 and IOP5 provided to be dedicated to the datatransmission for the spare memory cells.

[0074] Each spare memory cell column is constituted so that two memorycells store data of one bit as a whole. Two spare bit lines SBL areprovided per spare memory cell column. Selector 84 selects two out ofthe three spare memory cell columns to transmit data from these selectedcell columns to spare column-dedicated IO line pairs IOP4 and IOP5. Theselection of selector 84 is made in accordance with control signal RCONoutputted from CAM array 38 which detects redundancy. A spare bit lineto be used according to an input address is connected to the sparecolumn-dedicated IO line pair by selector 84.

[0075] If the number of spare memory cell columns is set equal to thatof spare column-dedicated IO line pairs, selector 84 may not beprovided. In this case, the data from spare memory array 12 is alloutputted up to a select section 100. Thereby, it is unnecessary toapply a redundancy detection result to the selector section of a bitline output section, which may possibly accelerate operation rate.

[0076] In the first embodiment, however, selector 84 is provided andselector 84 selects two out of the three spare memory cell columns whenconnecting the selected columns to the IO line pairs for the followingreason. If the number of IO line pairs increases, the area ofnonvolatile semiconductor memory device 1 disadvantageously increases byas much as the increased number of provided IO line pairs.

[0077] Selectors 81 to 83 and connection sections 91 to 96 shown in FIG.2 correspond to a part of read/write control circuit 30 shown in FIG. 1.In addition, selector 84 corresponds to a part of redundancy selectsection 32 shown in FIG. 1. Thus, selected memory cells are connected toa total of five IO line pairs.

[0078] Five IO line pairs IOP1 to IOP5 are connected to select andamplification section 40. Select and amplification section 40 includesselect section 100 which selects three out of five IO line pairs IOP1 toIOP5 in accordance with control signal RCON and sense amplifiers 101 to103 for reading the data of the memory cells connected to the IO linepairs selected by select section 100. The number of sense amplifiers isset 3 equal to that of data necessary to be outputted to terminals 111to 113.

[0079] The IO line pair to which a defective memory cell detected by CAMarray 38 shown in FIG. 1 is connected and the IO line pair connected toan unnecessary spare bit line are not connected to sense amplifiers 101to 103. Sense amplifier 101 to 103 are connected to the memory cellswhich store data corresponding to inputted addresses through thecorresponding IO line pairs.

[0080] If the memory cells connected to sense amplifiers 101 to 103 arenormal memory cells, sense amplifiers 101 to 103 are also connected to areference memory cell which is present in the corresponding referencecell column and compare current values carried to the two memory cells.

[0081] If the memory cells connected to sense amplifiers 101 to 103 arespare memory cells, sense amplifiers 101 to 103 compare current valuescarried to the two complementary memory cells.

[0082] As can be seen, in each spare memory cell column, two memorycells store data of one bit as a whole, dedicated IO line pairs forreading data from the spare memory cells are provided, and the sparememory cells are selected depending on which IO line pairs the senseamplifiers which detect current on the connected IO line pairs areconnected to.

[0083] With such a configuration adopted, it is possible to improve thereliability of the spare memory section. In addition, it is possible tosimultaneously read data from the normal memory cells and the sparememory cells and to thereby accelerate operation rate. Furthermore, bysimultaneously reading up to the data from the IO line pairs providedoutside of the memory cell array, it is possible to further acceleratethe operation rate.

[0084]FIG. 3 is a block diagram for describing a data write system ofnonvolatile semiconductor memory device 1 shown in FIG. 1.

[0085] With reference to FIG. 3, if nonvolatile semiconductor memorydevice 1 is MRAM, a path for accessing the spare memory cell columnschanges between data write and data read. The input data (three piecesof data in FIG. 3) are normally transmitted to write drivers 121 to 123and 131 to 133 for corresponding blocks and each of the correspondingwrite drivers is controlled to carry a current to desired bit line BL.

[0086] If the addressed normal memory cell to which data is to bewritten is in a defective column which is to be relieved and replaced bya spare memory cell column, data is written to a spare memory cell inplace of the normal memory cell.

[0087] Write data DIN is distributed to spare memory array 12 by adistribution circuit 150 based on control signal RCON which shows theredundancy detection result. At this moment, if the normal memory cellcorresponding to the address signal is defective, the write drivercorresponding to this defective memory cell is deactivated in the normalmemory cell region. Among write drivers 141 to 143 provided for thespare region, the write driver corresponding to the spare memory cell towhich data is to be written in place of the defective normal memory cellis activated. The write driver thus activated performs a data writeoperation in accordance with the data.

[0088] Each of the write drivers in the normal region may perform a datawrite operation even if its corresponding memory cell is a defectivememory cell. In this embodiment, however, the write driver correspondingto the defective memory cell is deactivated with a configuration to bedescribed later with reference to FIG. 5 so as to avoid increasing awrite current.

[0089] Inputted write data DIN is distributed to memory array 10 orspare memory array 12 in accordance with control signal RCON showing theredundancy detection result. If the address to which write data DIN isto be written corresponds to the defective memory cell, distributioncircuit 150 distributes write data DIN not to the corresponding normalmemory block in the normal memory array but to spare memory cell columns71 to 73. Further, corresponding one of write drivers 141 to 143 isactivated.

[0090]FIG. 4 is a circuit diagram showing the configurations shown inFIGS. 2 and 3 in more detail.

[0091]FIG. 4 typically shows normal memory cell block 51, reference cellcolumn 61, spare memory cell column 71 and their related circuits.

[0092] First, normal memory cells will be described. Normal memory cellblock 51 includes memory cells MC arranged in a matrix. One memory cellMC stores data of one bit. Write drivers 121 and 131 for data write andconnection section 91 for data read are connected to bit lines BLA andBLB. Write drivers 121 and 131 are arranged on the both ends of each ofbit lines BLA and BLB.

[0093] The direction of a current carried to bit lines when data “0” iswritten to memory cell MC is opposite to that of a current carriedthereto when data “1” is written to memory cell MC. Specifically, ifdata “1” is written to memory cell MC, a transistor 181 in write driver121 is set conductive and a transistor 192 in write driver 131 is setconductive. Thereby, a current is carried across bit line BLA in adirection from write driver 121 to write driver 131.

[0094] On the other hand, when data “0” is written to memory cell MC, atransistor 191 in write driver 131 is set conductive and a transistor182 in write driver 121 is set conductive. Thereby, a current is carriedacross bit line BLA in a direction from write driver 131 to write driver121.

[0095] Likewise, for bit line BLB, transistors 183, 184, 193 and 194 arecontrolled based on write data DIN. In FIG. 4, reference symbol W1denotes a signal which is activated when data “1” is written to memorycell MC and reference symbol W0 denotes a signal which is activated whendata “0” is written thereto. As can be seen, the transistors in writedrivers 121 are controlled to be activated in a reversed manner from thetransistors in write drivers 131.

[0096] In a standby state, in both write drivers 121 and 131, thetransistors may be activated to fix the potential of bit lines to groundpotential GND or all of transistors 181 to 184 and 191 to 194 may be setnonconductive to turn the bit lines in a floating state.

[0097]FIG. 5 is a circuit diagram for describing an example of a circuitin write driver 131, which controls deactivation when a spare cell isselected.

[0098] With reference to FIG. 5, a control unit 195 includes an ANDcircuit 196 which receives a control signal /HIT and a signal SW0, andan AND circuit 197 which receives control signal /HIT and a signal SW1.The output of AND circuit 196 is applied to the gate of transistor 191.The output of AND circuit 197 is applied to the gate of transistor 192.If CAM array 38 shown in FIG. 1 determines that the input addresscoincides with the address of a defective memory cell, the write driversfor the normal memory cells are deactivated to decrease powerconsumption. If control signal /HIT is deactivated to L level, thelevels of outputs of AND circuits 196 and 197 become L level to therebymake both transistors 191 and 192 nonconductive. As a result, bit lineBLA turns into a floating state.

[0099] With reference to FIG. 4 again, during data write, transistors171 to 174 become conductive and transistors 161 to 164 becomenonconductive. Further, digit line driver 155 activates one of digitlines WDL1 to WDL4 in accordance with a write address. At this time, aconnection gate 215 connects a spare bit line SBLA to spare bit lineSBLB.

[0100] During data read, transistors 161 to 164 become conductive andtransistors 171 to 174 become nonconductive. Digit line driver 155activates one of word lines WL1 to WL4 in accordance with a readaddress.

[0101] Connection section 91 includes a connection gate 211 which isprovided between bit line BLA and an IO line IO1A and the gate of whichreceives a select signal CSLA, and a connection gate 212 which isprovided between bit line BLB and an IO line IO1B and the gate of whichreceives a select signal CSLB. Select signal CSLA is outputted from adecoding circuit 221 included in column decoder 25 which decodes columnaddress CA. Select signal CSLB is outputted from a decoding circuit 222included in column decoder 25.

[0102] Reference cell column 61 includes reference memory cells MCR eachof which stores a reference value for determining the data ofcorresponding normal memory cell MC. The write and read of the referencevalue to each reference memory cell MCR are performed in the same manneras those of data to each normal memory cell MC. However, during dataread, the connection of the reference memory cell to the IO line isspecially contrived. A bit line BLR corresponding to a reference memorycell column is connectable to both IO lines IO1A and IO1B by connectionsection 92.

[0103] Connection section 92 includes a connection gate 213 which isconnected between bit line BLR and IO line IO1B and the gate of whichreceives a control signal SREFA, and a connection gate 214 which isconnected between bit line BLR and IO line IO1A and the gate of whichreceives a control signal SREFB.

[0104] Select signal SREFA is activated when select signal CSLA isactivated. Thereby, if bit line BLA is connected to IO line IO1A,reference bit line BLR is connected to IO line IO1B. As a result, anamplification section 104 detects the difference in current valuebetween a current carried to memory cell MC and that carried to memorycell MCR.

[0105] On the other hand, select signal SREFB is activated when selectsignal CSLB is activated. Therefore, if bit line BLB is connected to IOline IO1B, bit line BLR is connected to IO line IO1A. The reason forconnecting adjacent bit lines BLA and BLB to different IO lines is touniformly distribute the junction capacities of connection gates 211 and212 to the IO lines. In accordance with this rule, it is necessary toselectively connect reference bit line BLR to appropriate IO line.

[0106] Next, the spare memory cells will be described. In each sparememory cell column, two memory cells store data of one bit as a whole.

[0107] For example, complementary pieces of data are simultaneouslywritten to two memory cells SMCA and SMCB selected by digit line WDL1.Due to this, write driver 141 driving the bit lines is arranged only oneside of the memory array. Further, bit line SBLA and SBLB are connectedto each other by connection gate 215 during data write.

[0108] If data “0” is written to a memory cell, transistors 201 and 204are made conductive in write driver 141 and a current is carried frombit line SBLA to bit line SBLB. Conversely, if data “1” is written to amemory cell, transistors 202 and 203 are made conductive in write driver141 and a current is carried from bit line SBLB to SBLA. Since bit linesSBLA and SBLB are connected to each other on one side by connection gate215, the direction in which the current is carried to bit line SBLA andthat in which the current is carried to bit line SBLB during data writeare always opposite each other. As a result, complementary pieces ofdata are written to two spare memory cells selected by a digit line.

[0109] Spare memory cell columns 72 and 73, not shown, besides sparememory cell column 71 are arranged in nonvolatile semiconductor memorydevice 1. Selector 84 selects two out of the three spare memory cellcolumns to connect the selected spare memory cell columns to IO linepairs IOP4 and IOP5 dedicated to the data read operation for readingdata from spare memory cells.

[0110] During data read, connection gate 215 does not connect bit linesSBLA and SBLB in spare memory cell column 71 and different currents arecarried to spare memory cells SMCA and SMCB.

[0111] As shown in FIG. 4, in the memory cell arrays of MRAM, one normalmemory cell stores data of one bit by comparing the normal memory cellwith the reference memory cell which holds a reference value. Two sparememory cells store data of one bit as a whole. Namely, complementarypieces of data are written to two spare memory cells, respectively andthe two spare memory cells are connected to a sense amplifier, therebyreading the stored data of one bit. By so constituting, the spare memorycell region which is often arranged in the peripheral portion of thememory cell array is more resistant against a variation in finisheddimensions of elements and a success rate for replacing and relieving adefective memory cell by a spare memory cell thereby increases.

[0112]FIG. 6 is a circuit diagram showing the configuration of programarray 36 shown in FIG. 1.

[0113] With reference to FIG. 6, program array 36 includes a digit linedriver 301, write drivers 303, 305, and control circuits 302 and 306which control write drivers 303 and 305, respectively.

[0114] Program array 36 also includes bit lines 351 to 354, a sourceline 330, a write digit lines 331 to 335 and word lines 341 to 345.

[0115] Further, program array 36 includes MRAM memory cells 361 to 364provided corresponding to digit line 331 and word line 341. Likewise,memory cells are arranged corresponding to the other word lines anddigit lines and a memory cell array 307 is thereby constituted.

[0116] During data write, transistors 321 to 325 become conductive anddigit line driver 301 selectively activates digit lines 331 to 335.During data read, transistors 311 to 315 become conductive andtransistors 321 to 325 become nonconductive. Digit line driver 301selectively activates word lines 341 to 345 during data read.

[0117] Memory cell columns connected to bit lines 351 and 352 correspondto a region which stores flags each indicating whether or not a programset is used. Program addresses are stored in the other region.

[0118] In the program array, two memory cells stores data of one bit asa whole so as to secure high reliability as in the case of the sparememory cell array. Data write is realized by, for example, writingcomplementary pieces of data to memory cells 361 and 362. At thismoment, control circuits 302 and 306 control the directions of currentsin accordance with write data. Reference symbol W1 denotes a gate whichis activated when data “1” is written and W0 denotes a gate which isactivated when data “0” is written.

[0119] Program array 36 further includes sense amplifiers 395 and 396and control gates 391 to 394 which connect sense amplifiers to bitlines. If data is read from memory cells 361 and 362, connection gates391 and 392 connect bit lines 351 and 352 to sense amplifier 395,respectively. If digit line driver 301 activates word line 341, senseamplifier 395 detects the difference between a current carried intosource line 330 through memory cell 361 and a current carried intosource line 330 through memory cell 362. A detection result istransferred, as a signal P1, to CAM array 38 shown in FIG. 1. Likewise,if data is read from memory cells 363 and 365, then connection gates 393and 394 are made conductive, sense amplifier 396 detects a currentdifference and transfers a detection result, as a signal Pn, to CAMarray 38. This transfer operation is performed when a current is carriedto the chip, for example. After the transfer of the signals to CAM array38, CAM array 38 can detect the consistency between an input address anda program address at high rate.

[0120] In this case, by activating a control signal BR, the data whichis programmed in program array 36 once can be fixed to the data whichcannot be rewritten. Thereby, a high voltage is applied to bit lines fora selected word line and the lower resistance MTJ element of memory cell361 or 362 is destroyed. Likewise, the data can be fixed by destroyingthe lower resistance MTJ element of memory cell 363 or 364 storing aprogram address. If a high voltage SVCC is applied from the outside ofnonvolatile semiconductor memory device 1 through pad 34 shown in FIG. 1to activate control signal BR, high voltage SVCC is supplied to worddriver 305 as a power supply therefor. To destroy the MTJ elementincluded in, for example, memory cell 361, write driver 303 isdeactivated and high voltage SVCC is applied to bit line 351 by worddriver 305.

[0121]FIG. 7 shows the change of the resistance value of a normal MTJelement.

[0122] With reference to FIG. 7, a magnetic field H changes if a currentis carried to the digit line. The resistance of the MTJ element of thememory cell changes between high resistance Rmax and low resistanceRmin. If high voltage SVCC is applied, the MTJ element is destroyed andthe resistance value of the MTJ element becomes Rb 1 which is far lowerthan low resistance Rmin.

[0123]FIG. 8 shows the change of the resistance value of an MTJ elementafter data is fixed.

[0124] With reference to FIG. 8, once high voltage SVCC is applied tothereby destroy the MTJ element, the resistance value of the MTJ elementremains Rb 1 even if a current is carried to the digit line and magneticfield H changes. If replacement information is stored in two memorycells complementary to each other and the memory cell which is set atlow resistance Rmin is destroyed, the result detected by the senseamplifier is normal even when the resistance value of the complementarymemory cell is changed from Rmax to Rmin by the application of aferromagnetic field. That is, since resistance value Rb1 is lower thanboth Rmax and Rmin, it is possible to fix a read result by furtherdecreasing the resistance of the lower resistance-side memory cell.

[0125] As a result, even if a ferromagnetic field is applied duringtransport or the like after replacing and relieving a defective memorycell, the replacement information does not change.

[0126] With reference to FIG. 6 again, it is also possible to detectwhether or not an MTJ element is destroyed after a normal relievingstep. It is assumed that the MTJ element of memory cell 361 isdestroyed. In this case, while control signal BR is inactive, oppositedata may be written to memory cell 361 by an ordinary MRAM rewritemethod to determine whether or not the written data can be read as anexpected value. Specifically, memory cell 361 may be rewritten into ahigh resistance state and memory cell 362 may be rewritten into a lowresistance state.

[0127] If the written data can be read as the expected value, it can bedetermined that memory cell 361 is not destroyed. If opposite data iswritten to memory cell 361 and the state can be fixedly read, then itcan be determined that memory cell 361 is a destroyed program set.Thereby, if a failure which generates after a normal relieving step isto be relieved, it is possible to program a defective address in programarray 36 while avoiding the already destroyed program set.

[0128] As can be understood from the above, by preparing a flag for eachprogram set, it is possible to determine the used state of the programset. Further, by constituting program array 36 so that a high voltagecan be applied thereto, it is possible to fix the replacementinformation stored in program array 36 to one which cannot be rewritten.The fixing state can be detected by reading the flag for thecorresponding program set.

[0129]FIG. 9 is a circuit diagram showing the configuration of CAM array38 shown in FIG. 1.

[0130] With reference to FIG. 9, CAM array 38 includes a flag storagesection 401, an address storage section 402, a consistency detectionsection 403, and a storage section 404 which stores the location of aspare memory cell column to be used.

[0131] Flag storage section 401 includes five latch circuits 411 to 415corresponding to five program sets which store different replacementinformation. Address storage section 402 includes program sets 421 to425 corresponding to latch circuits 411 to 415, respectively.Consistency detection section 403 includes consistency detectionsections 431 to 435 corresponding to program sets 421 to 425,respectively. Storage section 404 includes storage units 441 to 445which are activated in accordance with the outputs of consistencydetection sections 431 to 435. The outputs of storage units 441 to 445become control signal RCON.

[0132] Signals P1 to Pn outputted from program array 36 as alreadydescribed above with reference to FIG. 6 are inputted into flag storagesection 401 and address storage section 402 and held in the latchcircuits. The output of flag storage section 401 is outputted toconsistency detection section 403 and to a selector 405.

[0133] Whether effective addresses are already stored in program sets421 to 425 can be read to the outside by outputting the outputs of latchcircuits 411 to 415 from a terminal PO through selector 405 and anoutput circuit 406. Thereby, if a replacement address is added, it ispossible to prevent data from being written to the already used addressset.

[0134] Selector 405 selects one of the outputs of latch circuits 411 to415 in accordance with a set address SETADD for specifying one ofprogram sets 421 to 425. Output circuit 406 is activated in accordancewith a signal FREAD activated in a test mode to thereby output theoutput of selector 405 to terminal PO.

[0135]FIG. 10 is a circuit diagram showing the configuration ofconsistency detection section 431 shown in FIG. 9.

[0136] With reference to FIG. 10, consistency detection section 431receives a flag signal FLAG corresponding to program set 421 in flagstorage section 402, the outputs of latches 452 to 45 n included inprogram set 421 and inputted address signal ADD. Latch 452 holds theleast significant bit of the replacement address and latch 45 n holdsthe most significant bit thereof.

[0137] Consistency detection section 431 includes consistency detectioncircuits 461 to 46 n each of which performs comparison between areplacement address outputted from program set 421 and an input addresssignal in every bit, and an AND circuit 470 receiving a signal FLAG andthe outputs of consistency detection circuits 461 to 46 n and outputtinga signal HITI.

[0138] With reference to FIG. 9 again, consistency detection sections431 to 435 determine whether the outputs of program sets 421 to 425 inwhich corresponding flags are activated coincide with inputtedaddresses. According to the determination results, selector 84 performsa select operation during data read.

[0139] With the configuration shown in FIG. 9, five program sets areprovided. With the configuration of the array shown in FIG. 2, bycontrast, three spare memory cell columns are provided. Two out of thethree spare memory cell columns are connected to IO line pairs IOP4 andIOP5. That is, the number of columns which are replaced simultaneouslyto correspond to one access is two and the number of the outputs ofconsistency detection sections 431 to 435 which are simultaneouslyactivated is a maximum of 2.

[0140] Here, selector 84 shown in FIG. 2 performs a select operation toconnect two out of three spare memory cell columns 71 to 73 to the IOline pairs in accordance with the contents held in storage units 441 to445 included in storage section 404. Further, to connect IO line pairsIOP1 to IOP5 to sense amplifiers 101 to 103, the IO line paircorresponding to the address of a defective column is made unconnectedand the data read from the spare bit line is transmitted to the senseamplifier through the spare column-dedicated IO line pair.

[0141] Similarly, during data write, the write driver for the bit lineconnected to the detected defective memory cell is deactivated and thewrite data is transmitted to the write driver for the spare bit line.

[0142] As described above, the number of program sets and that of sparememory cell columns do not always have a one-by-one correspondence. Thenumber of program sets can be arbitrarily selected relative to that ofredundant spare memory cell columns. By providing flag bits, it ispossible to detect an unused program set when a replacement address isadded. In addition, the flexibility for the selection of the number ofredundant memory cells and that of program sets each storing areplacement address increases.

[0143]FIG. 11 is a circuit diagram showing the configuration of selectand amplification section 40 shown in FIG. 1.

[0144] With reference to FIG. 11, select and amplification section 40includes a select section 100 and an amplification section 104. Selectsection 100 selects three out of the five IO line pairs in accordancewith control signal RCON.

[0145] To select the IO line pairs, a so-called shift redundancy methodis employed. Select section 100 includes a switching circuit 481 whichselects one of IO lines IO1A, IO2A and IO3A and connects the selected 10line to an IO line RIO1A, and a switching circuit 491 which selects oneof IO lines IO1B, IO2B and IO3B and connects the selected IO line to anIO line RIO1B.

[0146] Select section 100 also includes a switching circuit 482 whichselects one of IO lines IO2A, IO3A and IO4A and connects the selected IOline to an IO line RIO2A, and a switching circuit 492 which selects oneof IO lines IO2B, IO3B and IO4B and connects the selected IO line to anIO line RIO2B.

[0147] Further, select section 100 includes a switching circuit 483which selects one of IO lines IO3A, IO4A and IO5A and connects theselected 10 line to an IO line RIO3A, and a switching circuit 493 whichselects one of IO lines IO3B, IO4B and IO5B and connects the selected IOline to an IO line RIO3B.

[0148] Amplification section 104 includes a sense amplifier 101 whichdetects the difference between a current carried to the memory cellconnected to IO line RIO1A and that carried to the memory cell connectedto IO line RIO1B to thereby read stored data, a sense amplifier 102which detects the difference between a current carried to the memorycell connected to IO line RIO2A and that carried to the memory cellconnected to IO line RIO2B to thereby read stored data, and a senseamplifier 103 which detects the difference between a current carried tothe memory cell connected to IO line RIO3A and that carried to thememory cell connected to IO line RIO3B to thereby read stored data.

[0149] Switching circuit 481 includes a decoder 500 which decodescontrol signal RCON, connection gates 501, 502 and 503 which connect IOlines IO1A, IO2A and IO3A, respectively to IO line RIO1A in accordancewith the output of decoder 500. Decoder 500 decodes a specific bit ofthe IO line corresponding to a defective memory cell and a bit forspecifying a spare cell column including a spare memory cell whichreplaces the defective memory cell. Decoder 500 sets one of connectiongates 501, 502 and 503 in a connected state based on the decodingresult.

[0150] By providing the three connection gates per one input node of asense amplifier, it is possible to perform a two-stage shiftingoperation. As a result, it is possible to select three out of the fiveIO line pairs and connect the selected IO line pairs to the three senseamplifiers by using the shift redundancy method.

[0151] In the shift redundancy, three out of IO lines IO1A to IO5A areselected and the selected IO lines are connected to IO lines RIO1A toRIO3A, respectively, without changing the arrangement order of theselected IO lines. In addition, three out of IO lines IO1B to IO5B areselected and the selected IO lines are connected to IO lines RIO1B toRIO3B, respectively, without changing the arrangement order of theselected IO lines.

[0152] By adopting the shift redundancy configuration, it is possible toprevent the length of connection paths between the input nodes of thesense amplifier and IO lines IO1A to IO5A and IO1B to IO5B from greatlydiffering from one another. It is thereby possible to make load uniformand to make an operation margin uniform.

[0153] Second Embodiment

[0154]FIG. 12 is a block diagram of a data read system of a nonvolatilesemiconductor memory device according to a second embodiment of thepresent invention.

[0155] With reference to FIG. 12, the nonvolatile semiconductor memorydevice in the second embodiment differs from that shown in FIG. 2 inthat a memory array 10 a instead of memory array 10 and a spare memoryarray 12 a instead of spare memory array 12 are provided.

[0156] Memory array 10 a includes normal memory cell blocks 51 a to 53a, reference rows 601 to 603 provided to correspond to normal memorycell blocks 51 a to 53 a, and selectors 81 a to 83 a. The output ofselector 81 a is connected to IO line pair IOP1. The output of selector82 a is connected to IO line pair IOP2. The output of selector 83 a isconnected to IO line pair IOP3.

[0157] Spare memory array 12 a includes spare memory cell columns 71 ato 73 a, and a selector 84 a which selects one of spare memory cellcolumns 71 a to 73 a in accordance with control signal RCON. The outputof selector 84 a is connected to IO line pairs IOP4 and IOP5.

[0158] Since the configuration of select and amplification section 40 isthe same as that described with reference to FIG. 2, it will not berepeatedly described herein.

[0159] The second embodiment is the same as the first embodiment in thattwo spare bit lines SBL are arranged in each spare cell column and twospare cells store data of one bit as a whole. The second embodiment,however, differs from the first embodiment in that reference rows 601 to603 each holding a reference value during data read are arranged inparallel to the word lines of the normal memory cell blocks.

[0160] Selectors 81 a to 83 a are provided to correspond to normalmemory cell blocks 51 a to 53 a, respectively. In addition, IO linepairs IOP1 to IOP3 are provided to correspond to normal memory cellblocks 51 a to 53 a, respectively.

[0161] The output of selector 81 a is connected to IO line pair IOP1. Acorresponding memory cell in normal memory cell block 51 a is connectedto one of the IO lines in IO line pair IOP1 through selector 81 a. Acorresponding memory cell in reference row 601 is connected to the otherIO line in IO line pair IOP1 through selector 81 a.

[0162] The output of selector 82 a is connected to IO line pair IOP2. Acorresponding memory cell in normal memory cell block 52 a is connectedto one of the IO lines in IO line pair IOP2 through selector 82 a. Acorresponding memory cell in reference row 602 is connected to the otherIO line in IO line pair IOP2 through selector 82 a.

[0163] The output of selector 83 a is connected to IO line pair IOP3. Acorresponding memory cell in normal memory cell block 53 a is connectedto one of the IO lines in IO line pair IOP3 through selector 83 a. Acorresponding memory cell in reference row 603 is connected to the otherIO line in IO line pair IOP3 through selector 83 a.

[0164] In FIG. 12, a case where the three IO line pairs and the threenormal memory cell blocks are provided is shown. However, as long as thenumber of normal memory cell blocks is equal to that of corresponding IOline pairs, the number of normal memory cell blocks and that of IO linepairs may be larger or smaller than 3. An accessed memory cell in thenormal memory cell block is connected to one IO line in thecorresponding IO line pair and a memory cell in the correspondingreference row is connected to the other IO line in the corresponding IOline pair.

[0165] Selector 84 a selects a part of spare memory cell columns 71 a to73 a. Selector 84 a selects two out of the three spare memory cellcolumns in accordance with control signal RCON outputted from the CAMarray and connects the selected spare memory cell columns to two IO linepairs IOP4 and IOP5, respectively.

[0166] Each spare memory cell column is constituted so that two memorycells store data of one bit as a whole. Two spare bit lines SBL areprovided per spare memory cell column. Selector 84 a first selects twoout of the three spare memory cell columns to transmit data from theseselected spare memory cell columns to spare column-dedicated IO linepairs IOP4 and IOP5. The selection of selector 84 a is made inaccordance with control signal RCON indicating a redundancy detectionresult. A spare bit line to be used according to an input address isconnected to the spare column-dedicated IO line pair by selector 84 a.

[0167] If the number of spare cell columns is set equal to that of sparecolumn-dedicated IO line pairs, selector 84 a may not be provided. Inthis case, the data from spare memory array 12 a is all outputted up toselect section 100. Thereby, it is unnecessary to apply the redundancydetection result to the selector section of a bit line output section,which may possibly accelerate operation rate.

[0168] In the second embodiment, however, selector 84 a is provided soas to select two out of the three spare memory cell columns when eachselected memory cell column is connected to the IO line pair for thefollowing reason. If the number of IO line pairs increases, the area ofthe nonvolatile semiconductor memory device disadvantageously increasesby as much as the increased number of provided IO line pairs.

[0169] Thus, memory cells are connected to a total of five line pairs.Five IO line pairs IOP1 to IOP5 are connected to selection andamplification section 40. Select and amplification section 40 includesselect section 100 which selects three out of five line pairs IOP1 toIOP5 in accordance with control signal RCON, and sense amplifiers 101 to103 for reading the data of the memory cells connected to the IO linepairs selected by select section 100. The number of sense amplifiers isset 3 equal to that of data necessary to be outputted to terminals 111to 113.

[0170] The IO line pair to which a defective memory cell detected by theCAM array is connected and the IO line pair connected to an unnecessaryspare bit line are not connected to sense amplifiers 101 to 103. Senseamplifiers 101 to 103 are connected to the memory cells which store datacorresponding to inputted addresses through the corresponding IO linepairs.

[0171] If the memory cell connected to sense amplifiers 101 to 103 arenormal memory cells, sense amplifiers 101 to 103 are also connected to areference memory cell which is present in the corresponding referencememory cell column and compare current values carried to the two memorycells.

[0172] If the connected memory cells are spare memory cells, senseamplifiers 101 to 103 compare the values of currents carried to the twocomplementary memory cells.

[0173] As can be seen, in each spare memory cell column, two memorycells store data of one bit as a whole, dedicated IO line pairs forreading data from the spare memory cells are provided, and the sparememory cells are selected depending on which IO line pairs are connectedto the sense amplifiers which detect current on the connected IO linepairs.

[0174] By adopting this configuration, it is possible to improve thereliability of the spare memory section. In addition, it is possible tosimultaneously read data from the normal memory cells and the sparememory cells and to thereby accelerate operation rate. Furthermore, bysimultaneously reading up to the data from the IO line pairs providedoutside of the memory cell array, it is possible to further acceleratethe operation rate.

[0175]FIG. 13 is a circuit diagram for describing memory array 10 a andspare memory array 12 a described with reference to FIG. 12 in moredetail.

[0176] With reference to FIG. 13, description will be given of theconfigurations with respect to normal memory cell block 51 a and sparememory cell columns 71 a and 72 a shown in FIG. 12.

[0177] Normal memory cell block 51 a includes memory cells 611, 612, 614and 615. Reference row 601 provided adjacent to normal memory cell block51 a includes memory cells 613 and 616.

[0178] Write drivers 630 and 631 and a selector 651 are provided tocorrespond to normal memory cell block 51 a and reference row 601. Writedriver 630 includes transistors 681 to 684. Write driver 631 includestransistors 691 to 694. The driver is denoted by reference symbol W1which becomes conductive when data “1” is written. The driver is denotedby reference symbol W0 which becomes conductive when data “0” iswritten.

[0179] Two data read word lines are alternately connected to the memorycells in one row. Namely, a word line WL1A is connected to a memory cell611 and a word line WL1B is connected to a memory cell 614. Likewise, aword line WL2A is connected to a memory cell 612 and a word line WL2B isconnected to a memory cell 615. It is noted that a data write digit lineWDL1 is provided to be common to each memory cell row. Namely, memorycells 611 and 614 are connected to digit line WDL1 and memory cells 612and 615 are connected to digit line WDL2.

[0180] One word line is provided in each reference row. Namely, a wordline WL3 is connected to a memory cell 616 and a word line WL4 isconnected to a memory cell 613.

[0181] Next, a data read operation for reading data from normal memorycell block 51 a will be described. Data of memory cells 611 and 612 isread by detecting a current carried from a bit line BLAa to each sourceline. At this moment, the data of each of memory cells 611 and 612 iscompared with that of reference memory cell 616. Due to this, a signalREADA is activated to make transistors 666, 667 and 668 conductive. Ifdigit line driver 655 selects a row, memory cell 611 or 612 is selected.At this moment, digit line driver 656 selects word line WL3. As aresult, a current is carried to amplification section 104 through gatecircuits 771 and 772 included in selector 651, IO line pair IOP1 andselect section 100.

[0182] On the other hand, in order to read data from memory cells 614and 615, a signal READAB is activated to thereby make transistors 661,662 and 663 conductive. In order to select memory cell 614 or 615, digitline driver 655 activates word lines WL1B or WL2B. In order to comparethe reference memory cell with the selected normal memory cell, digitline driver 656 activates word line WL4 and selects memory cell 613.

[0183] Next, the spare memory cells will be described.

[0184] Spare memory cell column 71 a includes spare memory cells 617 to620. Spare memory cell column 72 a includes spare memory cells 621 to624.

[0185] A write driver 641 is provided to correspond to spare memory cellcolumn 71 a. Write driver 641 includes transistors 701 to 704. A writedriver 642 is provided to correspond to spare memory cell column 72 a.Write driver 642 includes transistors 705 to 708. Among transistors 701to 708, if the transistor becomes conductive when data “0” is written,the transistor is denoted by reference symbol W0. If the transistorbecomes conductive when data “1” is written, the transistor is denotedby reference symbol W1.

[0186] If data is written to spare memory cells, then transistors 643and 644 are made conductive, currents in opposite directions are carriedto two spare bit lines by write drivers 641 and 642 and complementarypieces of data are written to the two memory cells. Namely, spare memorycells 617 and 619 store data of one bit as one pair. Spare memory cells618 and 620 store data of one bit as one pair. Likewise, in spare memorycell column 72 a, two memory cells store data of one bit as a pair.

[0187] If data is read from memory cells 611 and 612, data is read fromspare memory cell column 71 a in parallel to the read of data frommemory cells 611 and 612. Namely, if memory cell 611 is selected inresponse to the activation of word line WL1A, then spare memory cells617 and 619 are selected and data is read from spare memory cells 617and 619 by amplification section 104 through selector 84 a, IO linepairs and select section 100.

[0188] Further, if data is read from memory cells 614 and 615, eitherword line WLL1B or WL2B is activated and data is read from spare memorycell column 72 a in parallel to the read of data from memory cells 614and 615.

[0189] As described so far, digit lines are provided to be common to thenormal memory cells and spare memory cells. Two word lines arealternately connected to the normal memory cells in one row. By thusconstituting the reference rows, it is possible to employ the referencememory cell connected to the bit line adjacent the bit line to which theselected normal memory cell is connected. Therefore, the read pathbecomes equal between the normal memory cells and the reference memorycells, thereby making it difficult to cause a data read error.

[0190] Third Embodiment

[0191] In recent years, a phase-changing memory has been proposed as anonvolatile semiconductor memory device. The phase-changing memory isalso referred to as “OUM (Ovonic Unified Memory)”.

[0192]FIG. 14 is a plan view showing the shapes of memory cells in thephase-changing memory.

[0193]FIG. 15 is a cross-sectional view taken along line A-A of FIG. 14.

[0194] With reference to FIGS. 14 and 15, a word line 801 is formed ofan n-type impurity region on a P-type substrate 806 and a p-typeimpurity region 805 is formed above word line 801. Substrate 806, wordline 801 and impurity region 805 form a vertical PNP type parasiticbipolar transistor.

[0195] A heater element 804 is formed above p-type impurity region 805,a chalcogenide layer 803 is formed above heater element 804 and a bitline 802 is formed above chalcogenide layer 803.

[0196] Chalcogenide is germanium-selenium-tellurium alloy. Even a smallamount of chalcogenide can be transformed between an amorphous state anda crystal state by heating the chalcogenide by a resistor. Theresistance of chalcogenide is high in an amorphous state and low in acrystal state.

[0197]FIG. 16 is an equivalent circuit diagram of the memory cell arrayshown in FIG. 14.

[0198] With reference to FIG. 16, a memory cell 810 includes achalcogenide layer 811 and a PNP type bipolar transistor 812. A memorycell is selected by a word line 801 and a current is carried from a bitline 802 to a collector line 807 of the selected memory cell. Dependingon the value of the current carried to collector line 807 and currentcarrying time, the quantity of emitted heat of a heater electrodeprovided in contact with chalcogenide layer 811 is controlled to make itpossible to transform the state of chalcogenide layer 811 between acrystal state and an amorphous state.

[0199]FIG. 17 is a circuit diagram showing a case where the presentinvention is applied to the phase-changing memory.

[0200] With reference to FIG. 17, memory cells MC arranged in a matrixare provided in a normal memory cell block 51 b. A reference cell column61 b which holds a reference value when data is read from normal memorycell block 51 b is provided adjacent to normal memory cell block 51 b.Two memory cells store data of one bit as a whole in a spare memory cellcolumn 71 b. Spare memory cells SMCA and SMCB hold complementary valuesto each other. As a result, a spare memory cell does not require areference memory cell and the reliability of the spare memory cellbecomes higher than that of a normal memory cell.

[0201] Word lines WL1 to WL4 are provided to be common to normal memorycell block 51 b, reference cell column 61 b and spare memory cell column71 b. Word lines WL1 to WL4 are driven by word line drivers 851 to 854,respectively. Word line drivers 851 to 854 are selectively activated bya word line decoder 850 in accordance with an address signal. Bit linesBLA, BLB, SBLA and SBLB are driven by a write driver 861 during datawrite. Write driver 861 includes transistors 871 to 878.

[0202] The gates of transistors 871 to 878 are driven by a write driverdecoder 860. Write driver decoder 860 changes the potentials of bitlines and driving time according to write information so as to changethe phase of the chalcogenide layer of each memory cell.

[0203] During data read, a corresponding bit line is selected by decoder880 and a read gate 862 and one of gate circuits 886 and 887 isconnected to one of IO lines in an IO line pair.

[0204] If signal CSLA is selected by a decoder gate 881, signal SREFA isactivated and a reference memory cell is connected to the other IO linein the IO line pair by a gate circuit 888.

[0205] Conversely, if signal CSLB is activated by decoder gate 882, bitline BLB is connected to one IO pair in the IO line pair by gate circuit887. In this case, signal SREFB is activated to make gate circuit 889conductive and bit line BLR is connected to the other IO line in the IOline pair.

[0206] In order to uniformly distribute the junction capacities of gatecircuits 886 and 887 connected to the IO line pairs, the bit lines andIO line pairs are alternately connected to one another. Due to this,reference bit line BLR is also connected to one of the IO line in the IOline pair to correspond to the selected normal memory cell column.

[0207] Since the spare memory cell columns are constituted so that twomemory cells store data of one bit as a whole, opposite pieces of dataare written simultaneously to the two memory cells selected by the sameword line. As in the case of the configuration described with referenceto FIG. 3, three spare memory cell columns are provided. FIG. 17typically shows one memory cell column 71 b. A selector 84 b selects twoout of the three spare memory cell columns and the selected spare memorycell column is connected to spare column-dedicated IO line pairs IOP4and IOP5.

[0208] In normal memory cell block 51 b which stores data of one bit permemory cell, an accessed memory cell is compared with a memory cell inreference cell column 61 b to thereby read data. If a word line isactivated, decoder 880 and read gate 862 select the bit line to whichthe accessed memory cell is connected. The selected bit line is alsoconnected to IO line pair IOP1. A precharge current is carried to thebit line and the selected memory cell through the IO line pair and thestate of a sense amplifier changes according to the resistance value ofthe selected memory cell. The memory cell in reference cell column 61 bis simultaneously selected by the same word line as that for theaccessed memory cell. Bit lines for the both memory cells are connectedto amplification section 104 and the state of the accessed memory celland that of the reference memory cell are compared with each other.

[0209] On the other hand, since the spare memory cell column isconstituted to store data of one bit by two memory cells as a whole, itdoes not require a reference memory cell. In this way, by constitutingthe redundancy section to hold and store complementary data of one bitin two memory cells, it is possible to operate the spare memory cellarray more stably even if there is a variation in finished dimensions ofelements between the access memory cells and the reference memory cells.

[0210] Although the present invention has been described and illustratedin detail, it is clearly understood that the same is by way ofillustration and example only and is not to be taken by way oflimitation, the spirit and scope of the present invention being limitedonly by the terms of the appended claims.

What is claimed is:
 1. A nonvolatile semiconductor memory devicecomprising: a plurality of normal memory cells each storing data of onebit in a nonvolatile manner; a plurality of spare memory cells each usedin place of a defective memory cell when the defective memory cell ispresent in said plurality of normal memory cells, and constituted sothat two spare memory cells store data of one bit as a whole; a controlcircuit, in accordance with an external access, selecting a first memorycell group corresponding to an address signal from among said pluralityof normal memory cells and selecting a second memory cell group fromamong said plurality of spare memory cells in parallel to selection ofsaid first memory cell group; and a select and amplification sectionselecting a read memory cell group in accordance with said addresssignal from among said first and second memory cell groups, andamplifying and outputting the data held in said read memory cell group.2. The nonvolatile semiconductor memory device according to claim 1,further comprising: a data line group for reading the data from saidfirst and second memory cell groups, wherein said select andamplification section includes: a plurality of sense amplifier circuitsas many as memory cells included in said read memory cell group; and aselect section selectively connecting a part of said data line grouptransmitting the data to be read in accordance with said address signal,to said plurality of sense amplifier circuits.
 3. The nonvolatilesemiconductor memory device according to claim 1, wherein said pluralityof normal memory cells are arranged in rows and columns, and saidnonvolatile semiconductor memory device further comprising: a pluralityof word lines provided along said rows of said plurality of normalmemory cells; a plurality of bit lines provided along said columns ofsaid plurality of normal memory cells; a plurality of reference memorycells provided adjacent to a region in which said plurality of normalmemory cells are arranged, arranged to form columns along a columndirection of said plurality of normal memory cells, and each holding areference value for determining a read value when the data is read fromeach of said normal memory cells; first and second data lines, one ofthe first and second data lines being connected to one of said pluralityof normal memory cells and the other being connected to one of saidplurality of reference memory cells; and third and fourth data linesconnected to first and second spare memory cells, among said pluralityof spare memory cells, forming a pair and storing predetermined data ofone bit as the pair.
 4. The nonvolatile semiconductor memory deviceaccording to claim 1, wherein said plurality of normal memory cells arearranged in rows and columns, and said nonvolatile semiconductor memorydevice further comprising: a plurality of digit lines each providedcorresponding to each of said rows of said plurality of normal memorycells; and a plurality of word lines, two word lines providedcorresponding to each of said rows of said plurality of normal memorycells, for selecting the rows during data read, said plurality of normalmemory cells in each row are alternately connected to corresponding twoof said word lines, and said nonvolatile semiconductor memory devicefurther comprising: a plurality of reference memory cells providedadjacent to a region in which said plurality of normal memory cells arearranged, arranged to form rows along a row direction of said pluralityof normal memory cells, and each holding a reference value fordetermining a read value when reading the data from each of said normalmemory cells.
 5. A nonvolatile semiconductor memory device comprising: aplurality of normal memory cells; a plurality of spare memory cells eachused in place of a defective memory cell when the defective memory cellis present in said plurality of normal memory cells; a first data linegroup for reading a first data group from said plurality of normalmemory cells in accordance with an external access; a second data linegroup for reading a second data group from said plurality of sparememory cells in parallel to reading of said first data group; and aselect and amplification section selectively amplifying and outputting aread data group in accordance with an address signal, from said firstand second data groups.
 6. The nonvolatile semiconductor memory deviceaccording to claim 5, wherein said select and amplification sectionincludes: a plurality of sense amplifier circuits as many as the dataincluded in said read data group; and a select section selectivelyconnecting a part of said first and second data line groups transmittingthe data to be read in accordance with said address signal, to saidplurality of sense amplifier circuits.
 7. The nonvolatile semiconductormemory device according to claim 6, further comprising: a redundancycontrol section receiving said address signal, and detecting whether anaddress corresponds to an address indicating said defective memory cell,wherein a plurality of data lines included in said first and second dataline groups are aligned in a predetermined order, and said selectsection shifts the data lines selected from among said first and seconddata line groups in accordance with an output of said redundancy controlsection without changing said predetermined order, and connects theselected data lines to said plurality of sense amplifiers.
 8. Anonvolatile semiconductor memory device comprising: a plurality ofnormal memory cells; a plurality of spare memory cells each used inplace of a defective memory cell when the defective memory cell ispresent in said plurality of normal memory cells; and a program arraystoring an address of said defective memory cell in a nonvolatilemanner, wherein said program array includes a plurality of program sets,each of said plurality of program sets has a first program unitconsisting of nonvolatile memory cells equal in structure to said normalmemory cells, and storing a flag bit indicating whether thecorresponding program set is already programmed to store the address ofthe defective memory cell, and a second program unit storing the addressof the defective memory cell, and said nonvolatile semiconductor memorydevice further comprising: a select circuit selecting a part of theplurality of flag bits corresponding to said plurality of program sets,respectively, in accordance with addresses of the program sets; and aterminal for reading an output of said select circuit to an outside ofthe nonvolatile semiconductor memory device.
 9. The nonvolatilesemiconductor memory device according to claim 8, wherein said programarray further includes: a voltage switching circuit selectively applyingan external high voltage to said first program unit so as toirreversibly destroy a nonvolatile memory cell included in said firstprogram unit so that the frag bit indicates that the correspondingprogram set is already programmed.
 10. The nonvolatile semiconductormemory device according to claim 8, wherein said plurality of sparememory cells are arranged to be divided into a plurality of replacementunits, and said plurality of program sets are fewer than said pluralityof replacement units.
 11. The nonvolatile semiconductor memory deviceaccording to claim 8, wherein said plurality of spare memory cells arearranged to be divided into a plurality of replacement units, and eachof said program sets further has a third program unit storinginformation for designating one of said plurality of replacement units.12. The nonvolatile semiconductor memory device according to claim 8,wherein each of said program sets further has a consistency detectionsection detecting whether an address corresponding to the storeddefective memory cell coincides with an input address, and saidnonvolatile semiconductor memory device further comprising a writedriver deactivating a write signal written to said normal memory cell inaccordance with an output of said consistency detection section.